1. Field of the Invention
This invention relates generally to the fabrication of high density MRAM arrays. In particular, it relates to process integration schemes that can improve the scalability of high density field induced MRAM arrays.
2. Description of the Related Art
MRAM (Magnetic Random Access Memory) is now a proven memory technology that possesses many advantages over competing technologies. The main concerns associated with MRAM technology are its scalability and cost competitiveness.
In its basic form, MRAM circuitry incorporates an MTJ (magnetic tunnel junction) cell as a memory storage device. An elementary implementation of an MTJ cell comprises two magnetized layers separated by an insulating layer. The relative directions of the magnetization of the two layers can be changed by an external magnetic field (hence the term, “field induced”) of the proper direction and magnitude. When such a magnetization change occurs it produces a corresponding resistance change in the cell. This can be detected as a variation in a voltage across the cell which, in turn, is interpreted as a change in the memory state of the cell. In a typical cell configuration in which the magnetization of one cell layer is fixed in space (pinned layer) while the other is free to move (free layer), the two possible relative directions of two magnetized layers are parallel and antiparallel, which create, respectively, low and high resistance states of the cell and are then interpreted as a zero and one in binary logic.
To form an MRAM device, a plurality of such MTJ cells are arrayed within an architecture whose design places individual MTJ cells in a regular two-dimensional array arranged in rows and columns. This cell array is coordinated with an adjacent orthogonal planar matrix of current carrying lines (see FIG. 1a, below) that is formed as two overlapping sets of parallel conducting lines, each set being orthogonal to the other and each set being vertically displaced from the other. These layers of lines are termed word lines and bit lines and the MTJ cells are typically located at their (vertically separated) points of intersection. Thus, when a particular pair of overlapping word and bit lines are carrying an electrical current of the proper magnitude, the MTJ cell located at their point of intersection is sufficiently perturbed by their magnetic fields to change the relative direction of its magnetization. To facilitate operation of the circuitry, the bit lines typically make electrical contact with an upper capping layer of the MTJ cell, while the word line makes contact with a conducting electrode (bottom electrode) that contacts the bottom of the MTJ cell. Thus, these lines not only activate the cells through their magnetic fields, but they are also used to implement voltage measurements across the cells.
FIG. 1a is a simplified schematic overhead illustration showing orthogonally overlapping word (22) and bit (30) lines at whose intersections MTJ cells (not shown) would be positioned. Five word lines and four bit lines are shown, forming a 4×5 array, but an actual N×M array would more typically have N (number of bit lines) between 32 and 98 and M (number of word lines) between 256 and 1024. At the terminal ends of each bit line, word line landing (or connecting) pads (20) are formed, which will be used to facilitate electrical connections between the word and bit lines. As will be shown in FIG. 1b below, in a side cross-sectional view of one end of an exemplary illustrative circuit, the bit lines (30) are formed above the word lines (22) and the landing pads (20) are below the bit lines.
The physical layout of this typical MRAM device architecture comprises two vertically separated but electrically interconnected levels of circuitry. An upper level contains the MTJ cells and associated orthogonal matrix of current carrying word and bit lines substantially as schematically illustrated in FIG. 1a. The lower level contains an integrated CMOS based circuit that provides access to particular cells in the upper level for memory storage and read-out purposes by allowing current to flow into the selected wires in the matrix as well as into electrodes that directly connect to MTJ cells. As we shall see, the prior art process integration schemes by which these levels are fabricated and interconnected can be made more efficient so that the manufacturing costs are reduced and circuit scalability is improved.
Referring now to FIG. 1b, there is shown a schematic side cross-sectional illustration of an exemplary prior art MRAM device that includes a lower CMOS level and an upper magnetic memory device level that, in this example, is based on an array of MTJ cells and the word and bit line formation of FIG. 1a. The memory level could be a level formed of other active devices than MTJ cells. It will be an object of the present invention to describe new process steps and to apply them to the fabrication of this device, specifically to the integration of the CMOS level with the magnetic device level, possibly with slight variations in form that will be described. FIG. 1b will show the device from a side view and identify its component parts. FIG. 2 will show an overhead view of the same device at a horizontal cross-sectional level. Following this, FIG. 3a-3g will describe the prior art process steps by which this device is fabricated. Reference will be frequently made to the formation of various current carrying elements in a “single damascene” or a “dual damascene” process. This is a method of forming patterned metal conducting lines or vias in dielectric layers that is well known in the art, wherein trenches are formed in the layer or layers at either a “single” depth or at two different, or, “dual” depths and a conducting metal layer is deposited within the trench. The trench may be clad (lined) with a diffusion barrier prior to the metal layer deposition, or the trench may be left unclad. Note also that, for ease of visualization, all of the figures show only a small section of what would be a large device array substantially symmetrically disposed in a horizontal plane. It is understood by those familiar with the art that, generally, although only two word lines will be shown in these illustrations, there would be a plurality of M parallel word lines (M between 256 and 1024). It is also known that although only one bit line will be shown, there would be a plurality of N parallel bit lines (N between 32 and 98), directed orthogonally to the M word lines. The M word line connection pads (20) shown located at the opposite ends of each bit line will essentially define the lateral extent of the fabrication.
A 4×5 array has been shown in FIG. 1a. It is also known that although only two MTJ devices will be shown, there would be a regular N×M array of such devices, with one device being formed at each intersection of a word line and a bit line. Similarly, although only one or two connecting vias will be shown, there would be as many vias as necessary to form similar connections to all word lines, bit lines, MTJ devices and interconnects within the CMOS level.
The device in FIG. 1b has been nominally subdivided into four regions, solely for purposes of visualization. The horizontal broken line, A, subdivides the device into an upper “magnetic device portion” and a lower CMOS level. The vertical broken line, B, divides the device into a portion called “device array,” which, in this example, includes the MTJ cells and connections leading to them, and a portion called “connections,” which contains vertical conductive connections (vias) between CMOS level conducting lines and magnetic device level bit lines.
The CMOS level contains dielectric layers (11), and conducting pads (12), (13) surrounded by the various structures that will allow current to be carried upward from the CMOS level to elements in the magnetic device level. Typically the conducting connecting pads (12), (13) have been formed in a Cu damascene process into trenches within a dielectric layer (11). Conducting pad (12) is a metal landing pad for providing convenient connections to MTJ devices, while conducting pad (13) is a word line landing pad for contacting conducting vias (16) that will ultimately connect word lines and bit lines.
A dielectric capping layer (14) forms the boundary between the CMOS level and the magnetic device level. Regions (15) are portions of a dielectric layer through which vias (16), (17) have been formed. Vias (16) will connect the landing pads (13) in the CMOS level to a word line layer connection landing pad (20) and thereafter through to a bit line (30). Unclad vias (17) will be extended upward through clad via (21) and will finally connect the bottom electrodes (26) of the MTJ cells at opening (25) to CMOS level landing pads (12).
A dielectric capping layer (18) forms a floor for the formation of word lines (22). The word lines have been clad (24) in a damascene process. The same damascene process and the cladding have also been used in forming word line connection vias (21) and word line layer metal landing pads (20). We shall see below, that the addition of cladding (24) may be necessary for the word lines (22), but not for the vias (21) and connection pad (20).
A dielectric layer (23) separates the word line layer from the MTJ cells (28) and the bottom electrodes (26) on which the MTJ cells are formed. Finally a dielectric layer (29) serves as a substrate on which to form the bit line (30), which is formed in a damascene process. A via (31) connects the bit line to the landing pad (20).
Referring to FIG. 2, there is shown, to clarify the geometry, a schematic overhead view of a horizontal cross-section through an intermediate level of the fabrication shown in the side view in FIG. 1b. The structures (20) are word line layer connection metal landing pads (see also (20) in FIG. 1a) that will be used to facilitate connections between the word line (22) and bit line (not shown in FIG. 2, but see (30) in FIG. 1a). The circular openings (21) are clad connection vias. The thin layers (24), surrounding (20), (21) and (22) are cladding layers formed during the Cu damascene WL construction.
In the following description, using FIGS. 3a-3g, we illustrate the process steps by which the prior art MRAM device of FIG. 1b is fabricated. These steps will allow us to point to the inefficiencies and disadvantages of the prior art methodology and will lay a foundation for us to more meaningfully describe the objects of the present invention and the methods and structures required to implement it. For simplicity, we begin our process flow using the metal level of an already fabricated CMOS substructure as a substrate on which to fabricate the MTJ memory level. By “metal level” we refer to the patterned and Cu damascened structure of lines and connections shown below line A in FIG. 1. The structures in this level are already connected to CMOS devices below (not shown) and it is these devices that will ultimately be interconnected with the MTJ memory level to be formed above.
Referring first to schematic FIG. 3a, there is shown an already fabricated layer of CMOS patterned metal (12), (13), typically formed in a Cu damascened configuration. In accord with a single Cu damascened formation, Cu (the metal) is deposited in patterned and etched dielectric insulation (11) and excess metal extending beyond the etched regions of the dielectric is removed by a CMP process. The resulting planar (and metal-free) surface is covered with a first thin dielectric/capping/etch-stop layer (14). The patterned metal includes conducting lines and interconnects. Everything below layer (14) can be thought of as the CMOS level, although the actual CMOS structures will not be illustrated. The MTJ memory level will be formed above layer (14). A blanketing dielectric layer (15) has been formed over the capping layer (14) which will serve as a surrounding medium for the MTJ fabrications and their write lines and bit lines.
Referring next to schematic FIG. 3b, there is shown the formation of interconnecting vias (16), (17) through the single blanket layer (15) using a single Cu damascene process that is well known in the art. The vias (17) will then be extended to go between the lower CMOS level and the upper MTJ level, The fabrication is then covered by a second thin capping layer (18) and a second blanketing dielectric layer (19). It is important to note that excess Cu must be removed by a CMP process to allow deposition of the second capping layer (18).
Referring next to schematic FIG. 3c, there is shown the application of a single Cu damascene process to create word lines (WL) (22) and word line connection metal landing pads (20) to connect the word line (WL) and the bit line (BIT), word line connection (WLC). The vias (21), which are clad (24), extend upward from vias (17) and now connect CMOS and individual MTJ devices. Typically, the word line (WL) (22) and word line connection (WLC) via (21) are formed and clad at the same time using a single mask. Therefore both the WL and the WLC have cladding materials, which are shown as (24). We shall see with respect to the second, third and fourth embodiments below, that the unnecessary cladding of the via (21) is eliminated by the use of two masking processes in a double damascene process. Elimination of unnecessary cladding materials is highly advantageous as structures continue to diminish in size, as these cladding materials can interfere with the magnetic properties of the devices that are nearby.
Referring next to schematic FIG. 3d, there is shown the fabrication of FIG. 3c with the formation of a third capping layer (23) which is opened at (25) to complete the interconnecting vias (17) and (21) through which the connections between subsequent bottom electrodes (BE) of MTJ cells and CMOS devices will be made.
Referring next to schematic FIG. 3e, there is shown the fabrication of FIG. 3d with the deposition of a bottom electrode (BE) layer (26) on which is then formed and patterned MTJ cells (28). Typically, the BE and the MTJ are formed in a single pump-down deposition process. Then the MTJ is patterned. After MTJ patterning, a dielectric protection layer (260) is deposited and this is followed by the BE patterning which is done by the use of a photomask and etch process.
Referring next to schematic FIG. 3f, there is shown the results of patterning the BE layer (26) of FIG. 3e, followed by the deposition of a blanketing dielectric refill layer (27) to isolate MTJ cells. The refill layer (27), which subsumes the protective layer (260) of FIG. 3e, is then planarized by a process of chemical mechanical polishing (CMP), leaving a smooth and planar upper surface.
Referring finally to schematic FIG. 3g, there is shown the fabrication of FIG. 1f on which a fourth protective dielectric layer (29) for bit line deposition by a double damascene process has been deposited. A via (31) is formed through (29), (27) and the third dielectric capping layer (23). This via will connect the word line connection pad (20) to the BIT line about to be formed. Additional openings in (29) have been made over the MTJ cells (28). Finally, a BIT line (30), using a dual damascene process, is formed over the entire fabrication. The lower surface of the BIT line contacts via (31) to enable a connection to the word lines.
The steps outlined above and described in FIGS. 3a-3g can be changed and the resulting process flow can be made more efficient, cost effective and scalable by addressing certain issues related to the damascene process that requires the cladding of lines and vias. Prior art attempts have already been disclosed in efforts to address some of the issues associated with MRAM fabrication. Kim et al. (U.S. Pat. No. 6,806,096) discloses a dual damascene process to pattern conductive lines and vias in an MRAM. Zhong et al. (U.S. Pat. No. 7,508,700) assigned to the same assignees as the present invention, discloses a dual damascene process to form vias and bit line contact pads. Park et al. (U.S. Pat. No. 6,849,465) teaches patterning a bottom electrode prior to depositing the soft magnetic layer of the MTJ. Kyler et al. (US Publ. Patent Appl. 2008/0296711) teaches forming a bottom electrode prior to forming the MTJ stack.
Although this prior art does describe certain elements of an MRAM fabrication, it does not teach methods that address the fabrication process steps as a whole so as to make the process flow simpler, more efficient and more readily scalable. That is the intent of the present invention.